31/01 – 7/02 Seminari per il corso Affidabilità di Sistemi Digitali

Nell’ambito del corso di Affidabilità di Sistemi Digitali, erogato per il corso di laurea magistrale in Ingegneria Elettronica, il prof. Marco Ottavi (ottavi@ing.uniroma2.it) organizza un ciclo di seminari di cui viene di seguito fornita l’agenda e gli abstract


mercoledì  29 gennaio, ore 11:00 Sala Riunioni R2
Logica Programmabile in Sistemi Safety Critical – Progettazione, Sviluppo e Test
Relatore: Ing. Massimo Fiorelli – Neat S.r.l (seminario annullato)

venerdì 31 gennaio ore 11:00 Sala Riunioni R2
Reliability of Computing Systems in the Era of Autonomous Vehicles and Supercomputers
Relatore:  Prof. Paolo Rech –  Federal University of Rio Grande do Sul, Porto Alegre, RS, Brazil

venerdì 31 gennaio ore 14:00 Sala Riunioni R2
Fault Tolerant and Secure Embedded Systems
Relatore:  Dr. Luca Cassano –  Politecnico di Milano

martedì 4 febbraio ore 11:00 Sala Riunioni R2
Rad-hard standard cells for space applications
Relatore:  Dr. Cristiano Calligaro –  RedCat Devices Srl, Milano, Italy

venerdì 7 febbraio ore 14:30 Sala Riunioni R2
High-Performance Embedded Computing in Space
Relatore: Dr. Gianluca Furano – European Space Agency

mercoledì 29 gennaio, ore 11:00 Sala Riunioni R2

Logica Programmabile in Sistemi Safety Critical – Progettazione, Sviluppo e Test

Relatore: Ing. Massimo Fiorelli Head of firmware engineering Neat S.r.l

I sistemi safety critical sono in grado di gestire funzioni sempre più complesse e diventano sempre più importanti nella vita di tutti i giorni.
Trasporti (auto, treni, aerei), apparecchi medicali, Impianti industriali, centrali nucleari sono solo alcuni esempi di settori in cui un malfunzionamento di un sistema può avere conseguenze catastrofiche.

Le architetture di questi sistemi hanno caratteristiche comuni e prevedono normalmente più unità di elaborazione che cooperano per realizzare la funzione di sicurezza.
Ciascuna unità di elaborazione, e quindi i suoi sottosistemi HW ed il suo SW, deve rispettare una serie di vincoli e adottare una serie di tecniche standardizzate per garantire l’adeguato livello di integrità della sicurezza del sistema (SIL).

Molto frequente ormai è l’utilizzo di dispositivi programmabili (FPGA) per l’ implementazione di funzioni critiche che necessitano di tempi di risposta veloci o per il controllo di numerosi GPIO.
Per questo motivo le nuove normative pongono molta attenzione sul processo di sviluppo basati su linguaggi di descrizione dell’hardware (VHDL, Verilog). Questo seminario presenterà il ciclo di vita di sistemi safety critical che utilizzano device FPGA: definizione dei requisiti, progettazione, implementazione, test e validazione.


Note sul relatore
L’Ing. Massimo Fiorelli è a capo dell’ ingegneria del firmware di Neat. Fiorelli è esperto di architetture di sistemi embedded e real time basati su microprocessori e logiche programmabili.
Neat S.r.l. è specializzata nella progettazione di prodotti HW e SW per applicazioni critiche in ambito avionico/aerospazio, ferrotramviario e industriale.

Venerdì 31 Gennaio ore 14:00 Sala Riunioni R2 Fault Tolerant and Secure Embedded Systems

Speaker: Dr. Luca Cassano Politecnico di Milano

The ubiquitous employment of embedded systems in safety-/mission-critical systems but also in consumer products and the growing interest in autonomous systems, e.g., autonomous cars and drones, impose designers to meet specific reliability-related requirements. Moreover, the distributed supply-chain which is commonly adopted to reduce design costs and time-to- market exposes digital systems to a number of security-related threats.

This talk will introduce the research activities carried out at Politecnico di Milano to design innovative solutions in the area of fault tolerance and security of digital circuits and systems. The first half of the talk will present an adaptive Convolutional Neural Network-based fault management scheme for image processing applications. The second half of the talk will focus on solutions to detect the presence and the activation of Hardware Trojans into CPU-based systems.

Speaker’s short bio

Since September 2017, Dr. Luca Cassano is an assistant professor at the Department of Electronics, Informatics and Bioengineering of the Politecnico di Milano. He received his BSc, MSc and PhD from the University of Pisa. Before his current position, Luca visited the Dipartimento di Automatica e Informatica of the Politecnico di Torino and the Cognitive Interaction Technology – Center of Excellence (CITEC) of the University of Bielefeld, both in 2012. Then, he worked as a post-doctoral researcher at the Istituto di Scienza e Tecnologie dell’Informazione “A. Faedo”, National Research Council in Pisa, and the Department of Electronics, Informatics and Bioengineering, Politecnico di Milano, and then as an Associate Member of the Technical Staff at Maxim Integrated.

The research activity carried out by Dr. Luca Cassano focuses on the design of dependable and secure embedded systems with particular emphasis on: i) tools for Fault Simulation, Automatic Test Pattern Generation, Testability Analysis and Fault Diagnosis, ii) techniques for fault detection, tolerance and management, and iii) Hardware Security, mainly focusing on Hardware Trojans.

martedì 4 febbraio ore 11:00 Sala Riunioni R2

Rad-hard standard cells for space applications

Speaker: Dr. Cristiano Calligaro RedCat Devices Srl, Milano, Italy

Semiconductor components to be used in space applications have as a major constraint the need to be resilient against radiations.
Total Ionizing Dose (TID) and Single Event Effects (SEE) come from energetic particles interacting with silicon devices and produce both hard errors (Latch-up, degradation of oxides) and soft errors (bit flip of memory elements and transient propagation).

To mitigate such effects very tailored design techniques are adopted (Radiation Hardening by Design or simply RHBD) making leverage on standard and well consolidated silicon process (mainly CMOS).
In this tutorial the major effects on the interaction between charged prticles and silicon devices will be presented together with the most common techniques to make a mitigation according to the expected mission (low orbits, high orbits, deep space). Design techniques at circuit level (smart schematics) and at layout level (robust layouts) will be mentioned with a specific focus on digital building blocks (standard cells, embedded SRAMs) used for larger mixed signal ASICs (microcontrollers, core processors, imagers, DSPs).

In the last part of the tutorial some “real world” examples will be shown together with a list of the major Free Open Source (FOS) CAD tools available.

Speaker’s short bio
Cristiano Calligaro received the laurea degree in Electronic Engineering and the Ph.D. degree in Electronics and Information Engineering from the University of Pavia (Italy) in 1992 and 1997 respectively. After obtaining the Ph.D. degree he moved to MAPP Technology. In 2006 he established RedCat Devices srl as a start-up. During his career he has been involved in memory design (volatile and non-volatile) both for consumer application (multilevel flash memories) and space applications (rad-hard memories) and software design for SEE evaluation using free CAD tools (Open Circuit Design). His current research interest is focused on rad-hard libraries for mixed signal ASICs, stand-alone memories (SRAMs and NVMs) and testing methodologies for rad-hard components. He holds 20 patents mainly in the field of multilevel NVMs and is co- author of more than 50 papers and one book (Rad-hard Semiconductor Memories, River Publishers). He has been coordinator of RAMSES and ATENA projects inside the Italy-Israel Cooperation Programme, SkyFlash project in the European FP7 Programme and EuroSRAM4Space project in the Eureka Eurostars2 Programme. He is IEEE Senior Member and Eureka Euripides reviewer.

venerdì 7 febbraio ore 11:00 Sala Riunioni R2    Anticipato a venerdì 31 gennaio

Reliability of Computing Systems in the Era of Autonomous Vehicles and Supercomputers

Speaker: Prof. Paolo Rech
Federal University of Rio Grande do Sul, Porto Alegre, RS, Brazil

Reliability is one of the major concerns for both safety-critical and High-Performance Computing applications. A neutron impact can generate faults in computing devices, leading to application crashes, wrong results, and system hangs. Several evidences showed that neutron-induced faults have corrupted large-server operations, have caused unexpected behaviors in airplanes, lead to car accidents … and have even influenced politics results.

In the talk we will briefly cover the effects of neutron impact on computing systems and applications. Particular emphasis will be given to self-driven cars, which is the newest trend in the automotive industry. We will present the results of several experiments on object- detection frameworks for automotive applications and show that neutrons can effectively change the way a vehicle senses objects, potentially leading to accidents.

Lately, novel architectural solutions, such as heterogeneous computing and mixed-precision architectures, have been introduced to increase devices computational efficiency. We will discuss if and how we can take advantage of these novel architectural solutions to improve applications reliability without unnecessary overhead. Particular attention will be given to the reliability of Xilinx Field-Programmable Gate-Arrays (FPGA), Intel Xeon Phis, NVIDIA Graphics Processing Units (GPUs), ARM embedded devices, and AMD heterogeneous devices.

Speaker’s short bio
Paolo Rech received his master and Ph.D. degrees from Padova University, Padova, Italy, in 2006 and 2009, respectively. He was then a Post Doc at LIRMM in Montpellier, France. Since 2012 Paolo is an associate professor at UFRGS in Brazil. He is the 2019 Rosen Scholar Fellow at the Los Alamos National Laboratory and he is actively collaborating with major research centers as Jet Propulsion Laboratory and Rutherford Appleton Laboratory as well as silicon industries as NVIDIA, AMD, and ARM. His main research interests include the evaluation and mitigation of radiation-induced effects in large-scale HPC centers and in autonomous vehicles for automotive applications and space explorations.

venerdì 7 febbraio ore 14:30 Sala Riunioni R2 High-Performance Embedded Computing in Space

Speaker: Dr. Gianluca Furano European Space Agency

Future missions, such as active debris removal for cleaning up the low Earth orbit environment, will rely on novel high-performance avionics to support advanced image processing algorithms with substantial workloads. However, when designing new avionics architectures, constraints relating to the use of electronics in space present great challenges, further exacerbated by the need for significantly faster processing compared to conventional space-grade central processing units. With the long-term goal of designing high performance embedded computers for space, in this seminar, an extended study and tradeoff analysis of a diverse set of computing platforms and architectures (i.e., central processing units, multicore digital signal processors, graphics processing units, and field-programmable gate arrays, AI accelerators) will be presented.

Speaker’s short bio
Gianluca Furano, works in European Space Agency’s in Data System Division in March 2003. He is in charge for research and development activities and for supporting ESA projects and missions in the field of spacecraft data systems and the related architectures.
Among’s Gianluca interest are in ESA are on-board computers and their major components, such as microprocessors and support components, meeting very stringent requirements in terms of radiation tolerance, reliability, availability, and safety; key avionics building blocks such as platform mass memories, remote terminal units, on-board buses and data networks; on-board and space to ground data communication protocols including protocol security aspects.
Gianluca also provides support to European standardisation (CCSDS, ECSS) in areas such as telemetry, telecommand and on-board data, wireless and monitoring & control interfaces.